Variable Input Delay CMOS Logic for Low Power Design
نویسندگان
چکیده
منابع مشابه
Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits
A gate that offers different delays for different input-output paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper,...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2009
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2009.2027567